A new power analysis resistant SRAM cell

Abstract

The power consumption of a standard SRAM during read/write operations is dependent on the address applied, the data accessed, and the type of access (read/write). The power analysis resistant SRAM structure [1] developed during the Project “SCARD” (Side Channel Analysis Resistant Design Flow) of the European Community 6. Framework Program reduces the dependency of power consumption on data and address compared to standard SRAM at the expense of higher power and silicon area consumption. In this work a new SRAM primitive cell structure is proposed to reduce the power consumption and its dependency to data to be written.