Abstract
123 decision diagram is a very effective PTL synthesis tool based on binary decision diagram. It realizes a logic function using NMOS pass transistors with CMOS restoring buffers. In this paper the 123 decision diagram is applied to realize CMOS pass transistor logic circuits without restoring buffers. Cell circuits for the 4 bit adder is realized with the CMOS pass transistors using the 123 decision diagram and 4 bit adder is completed by combining the cells.
Keywords
NMOS logic
CMOS
Pass transistor logic
Binary decision diagram
Adder
Transistor
Computer science
Logic gate
Electronic circuit
Logic family
Diagram
Resistor–transistor logic
Electronic engineering
Sequential logic
Digital electronics
Logic synthesis
Electrical engineering
Engineering
Algorithm
Subject Areas
VLSI and Analog Circuit Testing
·Hardware and Architecture ·Physical Sciences
Low-power high-performance VLSI design
·Electrical and Electronic Engineering ·Physical Sciences
Embedded Systems Design Techniques
·Hardware and Architecture ·Physical Sciences
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