Abstract
This paper deals with a fully differential (FD) operational amplifier (opamp) consists of double folded cascode and class AB output with continuous time common mode feedback (CMFB) network. The opamp is designed in 0.18 μm CMOS technology in Cadence Spectre Circuit Simulator with 1.8 V supply. In this single supply, opamp has 117 dB gain, 65-degree phase margin, 72 dB common-mode rejection ratio (CMRR) for 2pF load with a power consumption of only 1.2 mW. This topology is more suitable for high-speed pipeline Analog-to-Digital converters (ADCs) with foreground calibration, when compared to conventional designs, enabling operation at higher clock frequencies as the class AB stage causes the slew limiting in the first stage and power dissipation is decreasing.
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