Neuromorphic Logic Gates Design

Abstract

In this paper, digital logic circuits AND and OR gates, which are the basis of hardware design units, are designed to consume 9.63nW of power using a single neuron structure. Without changing the topology of the neuron circuit the transition between the gates can be adjusted by changing only the bias voltage value. Since the designed neuron circuit has the ability to exhibit dynamics such as leakage, thresholding and refractory period in the biological neuron, different information coding methods can be applied by changing the circuit bias voltages. The presented neuron circuit consumes a very low power of 9.63nW due to its operation in the sub-threshold region. The proposed circuit structure is designed with UMC 130nm CMOS technology. Simulation results were obtained using Cadence Spectre.